Generally, a lateral diffused metal oxide semiconductor (LDMOS) device, which is a high voltage MOS device, is used as a power semiconductor device.
A device that can operate at a high voltage close to a theoretical breakdown voltage of a semiconductor is preferred as an ideal power semiconductor device. Accordingly, in a case where an external system using a high voltage is controlled by an integrated circuit (IC), the IC needs a high voltage control device built therein and configured to have a high breakdown voltage.
That is, in the case of a drain or source of a transistor to which a high voltage is directly applied, it is required that a punch through voltage between the drain/source and a semiconductor substrate and a breakdown voltage between the drain/source and a well or substrate be higher than the high voltage.
Among those high voltage semiconductor devices, the LDMOS device has a structure suitable for a high voltage because channel region and drain electrode thereof are separated with a drift region disposed therebetween and controlled by a gate electrode.
FIG. 1 is a sectional view of an LDMOS device according to the related art.
Referring to FIG. 1, the related art LDMOS device includes a first well 12 formed in a substrate 10, a field oxide 17 formed on a surface of the substrate 10, and source region 15 and drain region 16 formed in the surface of the first well 12 at both sides of the field oxide 17. The source region 15 and the drain region 16 are isolated at both sides of the field oxide 17 by the field oxide 17. During formation of the field oxide 17, a gate oxide 18 is formed on the surface of the substrate 10 at both sides of the field oxide 17.
A gate electrode 19a is formed on the gate oxide 18, and a field plate 19b is formed on the field oxide 17 and connected with the gate electrode 19a. 
In FIG. 1, the symbol ‘L’ indicates a width of the field oxide 17, and a half pitch ‘HP’ indicates a distance between the source region 15 and the drain region 16.
The field plate 19b lowers a strong electric field at an edge of the gate electrode to increase the breakdown voltage, and decreases the resistance of the first well 12 to lower the On resistance ‘Ron’ of the LDMOS device.
To increase the breakdown voltage of the LDMOS device in the related art, there is a method of increasing the width ‘L’ of the field oxide 17. However, increasing the width ‘L’ causes the half pitch to be increased and the electric field at the edge of the gate electrode to also increase, so that the occurrence probability of a breakdown at the surface is increased and thus the On resistance ‘Ron’ is increased.
Also, because the related art LDMOS device separates the channel region and the drain electrode by a drift region and controls the drain current by a single gate, the drift region has a large On resistance and is not suitable for large current operation.